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How to understand 140ERT85420 clock SYNC and status report

Summary:
 
There are two bits of the EFB status for the ERT clock situation, which had been explained in user manual, here I give a complete explanation for them, and give a example when the GPS receiver send a error frame with leap second.
 
 
Solution:
 
Static notes in user manual for the two bits of EFB status:

Here is the dynamic of the two bits:

Comments for them:
 
  1. The 140ERT85420 can be synchronized by DCF77 and IRIG-B, the previous notes is just for DCF77, for IRIG-B, one frame is one second, and synchronized every second.
  2. IRIG-B frame is one second, DCF frame is one minute, so the resolution of IRIG-B is better than DCF.
  3. There is no error bit set in 10 minutes, because the module can keep running the clock by internal 32-bits timer, which had a good resolution in 10 minutes.
  4. The bit 2-TE will be set after 10 minutes, and bit 3-TU will not be set before “Validity Reserve” (Default is 1 hour), that the module can be synchronized if the clock signal is valid again, valid means the frame is correct and which is continuing with the clock in the module running.
  5. After the “Validity Reserve” time out, the module will give up the internal clock which is running without synchronization. Then initialized with the external signal.
 
Example: 2015-7-1 8:00 AM, there is a leap second happened, there is a issue in one customer site, the GPS receiver send a frame with a external second without leap indication. So ERT detected the frame as a error frame, and set bit 2-TE at 8:09, which reported by SCADA; after one hour the bit 3-TU is also set, then cleared after 2 minutes.
 
  1. The ERT will detect the frame with a extended second without leap indicated as a error frame;
  2. Error bit 2-TE will be set after 10 minutes;
  3. The bit 2 – TE will be always set in the following one hour even though the external signal is “correct” after the minute with “leap”. Because the following frame is delayed with one second with the clock in module. So from module side, the external signal is not continued with the clock in the module. So it will be recognized as error frame.
  4. After about one hour, the ERT will give up the internal clock and synchronize with the external signal.
  5. Different ERT module clear the error bits at different time, one is at 9:10, another is 9:05, because the internal timer of module is running, they are different situation, so some of the module will be deviated one second, it is matched the one second delay because of leap second. So the external signal will be detected as continuing, then ERT will recognize the external as valid.
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