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1. Set the command register bit 13 (allow user logic mismatch) in the Primary.
2. Stop the Standby PLC , load the optimized project and place back into run.
3. The Standby PLC should have come up in Standby mode. Verify that it did and force a switch over.
4. Perform a key switch transfer from the new optimized Primary to the Standby.
5. Verify that the standby is back online and force another switch over.
6. Reset Command Register bit 13 back to 0.
7. Verify that both the Primary and Standby PLCs are online.